Magnetic memory

ABSTRACT

A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2017-178264, filed on Sep. 15,2017, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to magnetic memories.

BACKGROUND

Recently, research and development of magnetic memories (magnetic randomaccess memories (SOT-MRAMs)) that perform spin orbit torque (SOT) writeoperations has been actively performed. A memory element included in anSOT-MRAM has a structure in which magnetic tunnel junction (MTJ)elements each having a multilayer structure including a storage layer, anonmagnetic layer, and a reference layer are disposed on a conductivenonmagnetic layers (also called “SO layers”). The magnetizationdirection of each storage layer is switched by causing a current to flowthrough the conductive nonmagnetic layer. A read operation is performedby causing a read current to flow between the conductive nonmagneticlayer and the reference layer through the storage layer and thenonmagnetic layer.

Magnetic memories that perform a write operation using spin transfertorque (STT) are also known (STT-MRAMs). A memory element of an STT-MRAMincludes MTJ elements each having a multilayer structure including astorage layer, a nonmagnetic layer, and a reference layer. Themagnetization direction of the storage layer is switched by causing awrite current to flow between the storage layer and the reference layervia the nonmagnetic layer. A read operation is performed by causing aread current to flow between the storage layer and the reference layervia the nonmagnetic layer.

Since the read current path and the write current path are the same inthe STT-MRAM, the element characteristics may vary if the device isminiaturized. Therefore, it is difficult to have enough margins amongthe read current, the write current, the current of the transistorconnected to the MTJ element for selecting the MTJ element, and thebreakdown current of the MTJ element by reducing the variations in therespective currents.

In the SOT-MRAM, the read current path is different from the writecurrent path. Therefore margins to deal with the variations in therespective currents are relatively large. Thus, variations of the readcurrent, the current of the transistor connected to the MTJ element forselecting the MTJ element, the breakdown current that may breaks thenonmagnetic layer of the MTJ element, the write current, and theelectromigration current flowing through the SO layer may be allowed tosome extent. The SOT-M RAM thus may have relatively broad margins todeal with variations in currents even if the memory elements areminiaturized (to improve the capacity of the memory). This is anadvantage of the SOT-MRAM to the STT-MRAM.

However, the cell area of the SOT-MRAM including the memory elements isas large as 12 F², F being the minimum feature size, and the writeefficiency (=Δ/Ic) of the SOT-MRAM is about 0.3, which is not so good.Thus, the SOT-MRAM is inferior in the cell area and the write efficiencyto the STT-MRAM. These problems need to be solved.

An SOT-MRAM is known, which has a reduced cell area. The SOT-MRAMincludes a memory cell in which a string of MTJ elements (memoryelements) is disposed on an SO layer. The cell area of the SOT-MRAM withsuch a structure is reduced to 6.75 F² per one bit (one memory element),which enables to produce a large-capacity voltage-controlled magneticmemory. In order to employ this structure, however, a voltage assistedmagnetic anisotropy control technique, which changes the magneticanisotropy (coercive force) of the storage layer by applying a voltageto the MTJ element, is preferably used in the SOT write operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a photograph for explaining a problem of a memory cellincluded in an SOT-MRAM.

FIG. 2 is a graph showing the dependency of the spin Hall angle to thethickness of the conductive layer.

FIGS. 3A to 3C are a diagram showing the changes in SOT switchingcurrent density when the voltage anisotropy effect is used.

FIG. 4 is a perspective view of a memory cell included in a magneticmemory according to a first embodiment.

FIG. 5 is a cross-sectional view of a memory cell included in a magneticmemory according to a modification of the first embodiment.

FIG. 6 is a diagram showing the dependency of the write current densityto the thickness of the Ir₉₀Ta₁₀ layer.

FIG. 7 is a perspective view of a memory cell included in a magneticmemory according to a second embodiment.

FIG. 8 is a cross-sectional view of a magnetic memory according to amodification of the second embodiment.

FIG. 9 is a diagram showing the result of measurements of switchingcurrent density Jc in the magnetic memory according to the modificationof the second embodiment.

FIG. 10 is a perspective view of a memory cell included in a magneticmemory according to a third embodiment.

FIG. 11 is a diagram for explaining a write method of the magneticmemory according to the third embodiment.

FIG. 12 is a diagram for explaining the write method of the magneticmemory according to the third embodiment.

FIG. 13 is a diagram for explaining the effect of the magnetic memoryaccording to the third embodiment.

FIG. 14 is a diagram for explaining the effect of a magnetic memoryaccording to a modification of the third embodiment.

FIG. 15 is a perspective view of a magnetic memory according to a fourthembodiment.

DETAILED DESCRIPTION

How the present invention has been conceived is first described beforeembodiments of the present invention are described.

As described above, the SOT-MRAM is inferior in write efficiency to theSTT-MRAM, and needs to improve the write efficiency. The writeefficiency is defined by dividing thermal stability Δ (=E/kT) by averagewrite current Ic (=Δ/Ic), where E is the height of energy barrier whenthe spin of the storage layer is parallel and antiparallel to the spinof the reference layer, Ic is an average value of the currents Ip andTap ((Ia+Ip)/2) in a case where the spin of the storage layer is changedfrom a parallel state to an antiparallel state and a case where the spinis changed from an antiparallel state to a parallel state. The writeefficiency of the SOT-MRAM needs to be improved.

FIG. 1 is a photograph of a cross-section around an MTJ element of amemory cell included in an SOT-MRAM that is actually fabricated, takenby a transmission electron microscope (TEM). The MTJ element included inthe memory cell is disposed on a conductive layer (SO layer) of Tahaving a thickness of 9.7 nm. As can be understood from FIG. 1, thesurface of the conductive layer is oxidized in a region other than aregion immediately below the MTJ element, where the conductive layer andan interlayer insulating film are in contact with each other, and thethickness of the region is reduced from 9.7 nm to 5.3 nm. The thicknessof the oxidized portion of the layer thus is 4.4 (=9.7−5.3) nm.

FIG. 2 shows the result of measurements proving the dependency of thespin Hall angle θ_(SH) to the thickness of a conductive layer includinga nonmagnetic heavy metal element. The conductive layer of themeasurements shown in FIG. 2 includes β-Ta. The write current density Jc(=Ic/cross-sectional area of SO layer) is proportional to the absolutevalue of the spin Hall angle θ_(SH).Jc=k·|θ _(SH)|Where k denotes a proportional constant. Therefore, if the thicknesst_(Ta) of the SO layer is reduced from 10 nm to 6 nm, for example, theaverage value of the write current I_(c) is reduced to 1/2.8. Thus, inorder to reduce the write current, the thickness of the conductive layermay need to be reduced. However, as described above with reference toFIG. 1, if the thickness of the conductive layer is reduced to 6 nm, thethickness of the region in the conductive layer other than the regionwhere the MTJ element is formed is reduced to 1.6 (=6−4.4) nm. Thisincreases the resistance of the conductive layer, and the function as anelectrode may be lost.

There is another problem. A voltage assisted magnetic anisotropy controltechnique is used for controlling an SOT-MRAM including a memory cell inwhich a string of MTJ elements is disposed on an SO layer. Acharacteristic of the voltage assisted magnetic anisotropy controltechnique is shown in FIGS. 3A to 3C. If a voltage of +1 V is applied toan MTJ element of the SOT-MRAM, the current density in the SO layerrequired to switch the magnetization of the storage layer of the MTJelement increases (FIGS. 3A and 3C), and if a voltage of −1 V is appliedto the MTJ element, the current density in the SO layer required toswitch the magnetization of the storage layer of the MTJ elementdecreases (FIGS. 3B and 3C). In this architecture of SOT-MRAM, thememory elements (MTJ elements) may be arranged with a high density, anda write operation may be simultaneously performed with a voltage of onepulse applied to the memory elements to switch the magnetization of thestorage layer of the MTJ element. Therefore, the power consumption maybe reduced. However, if a difference in write current density between aselected memory element and a non-selected memory element is smallerthan variations in write current density among the memory elements, awrite disturb error (WDE) may be caused. Although a voltage of ±1 V isapplied to the MTJ element in the above description, the voltage of ±1 Vis too much for an MTJ element having very thin films, and may cause abreakdown of the tunnel barrier. In other words, reliability of the MTJbecomes lower.

As described above, in order to reduce the write current, a materialhaving a large spin Hall angle θ_(SH) is preferably used. Known examplesof such a material are Ta, W, Re, Os, Ir, Pt, Au, Ag, alloys of thesematerials, and Cu—Bi. If a β-W film is formed in the noble gas Ar withoxygen (O₂), a maximum value at present θ_(SH)=−0.5 may be obtained(Nature Comm. DOI:10.1038/ncomms10644). According to a recent report,the spin Hall angle θ_(SH) of about 0.5 is obtained by Au_(0.9)Ta_(0.1)(Au with 10% of Ta) having a thickness of 10 nm (Intermag2017AM-01 bySpintec (Fert, Jaffres)).

The inventors of the present invention have studied hard to invent amagnetic memory with good write efficiency, which is obtained by usingthe voltage assisted magnetic anisotropy control technique. Embodimentsof such a magnetic memory will be described below.

A magnetic memory according to an embodiment includes: a first terminal,a second terminal, and a third terminal; a nonmagnetic conductive layerincluding a first region, a second region, and a third region, thesecond region being disposed between the first region and the thirdregion, the first region being electrically connected to the firstterminal, and the third region being electrically connected to thesecond terminal; and a magnetoresistive element disposed to correspondto the second region, including a first magnetic layer electricallyconnected to the third terminal, a second magnetic layer disposedbetween the first magnetic layer and the second region, and anonmagnetic layer disposed between the first magnetic layer and thesecond magnetic layer, the conductive layer including at least one of analloy including Ir and Ta, an alloy including Ir and V, an alloyincluding Au and V, an alloy including Au and Nb, or an alloy includingPt and V, each of the alloys having an fcc structure.

(First Embodiment)

A magnetic memory according to a first embodiment will be described withreference to FIG. 4. The magnetic memory according to the firstembodiment is an SOT-MRAM including at least one memory cell. FIG. 4shows such a memory cell 10. The memory cell 10 includes nonmagneticconductive layers (SO layers) 12 a and 12 b, a magnetoresistive element(for example, an MTJ element) 20 disposed on the conductive layer 12 a,which serves as a memory element, a switching element 30, and a wiringline 40. The conductive layer 12 b is connected to the conductive layer12 a. The conductive layer 12 a has a terminal (first terminal) 13 a,and the conductive layer 12 b has a terminal (second terminal) 13 b. Theconductive layer 12 b may be eliminated. In such a case, the terminal 13b is provided to the conductive layer 12 a, and the MTJ element 20 isdisposed in a region of the conductive layer 12 a between the terminal13 a and the terminal 13 b. The conductive layers 12 a and 12 b areconductive nonmagnetic layers, which generate a spin current when acurrent flows through them, to apply a spin obit torque (SOT) to astorage layer of the magnetoresistive element. Thus, the conductivelayer 12 a is a conductive nonmagnetic layer having a spin orbitcoupling function. Although a transistor is illustrated as the switchingelement 30 in FIG. 4, any switching element other than a transistor,which is turned on or off based on a control signal, may be used.

The magnetoresistive element 20 includes a storage layer (secondmagnetic layer) 21, in which the magnetization direction may be changed,a reference layer (first magnetic layer) 23, in which the magnetizationdirection is fixed, and a nonmagnetic layer (first nonmagnetic layer) 22disposed between the storage layer 21 and the reference layer 23. Thestate “the magnetization direction may be changed” means that, after awrite operation is performed, the magnetization direction may bechanged, and the state “the magnetization direction is fixed” meansthat, after a write operation is performed, the magnetization directionis not changed. The storage layer 21 is connected to the conductivelayer 12 a, and the reference layer 23 is connected to the wiring line40. One (terminal) of the source and the drain of the transistor 30 isconnected to the terminal 13 a of the conductive layer 12 a. The other(terminal) of the source and the drain and the gate (control terminal)of the transistor 30 are connected to a control circuit, which is notshown. The terminal 13 b of the conductive layer 12 b is grounded asshown in FIG. 4, or connected to the control circuit. The controlcircuit is also connected to the wiring line 40.

In this SOT-MRAM, a write operation is performed by causing, by means ofthe transistor 30, a write current I_(w) to flow through the conductivelayers 12 a and 12 b between the terminal 13 a and the terminal 13 b,and a read operation is performed by causing, by means of the transistor30, a read current I_(r) to flow through the terminal 13 a, theconductive layer 12 a, the magnetoresistive element 20, and the wiringline 40. Thus, the write current path and the read current path aredifferent from each other.

When the write current I_(W) flows through the conductive layer 12 a inthe write operation, spin-polarized electrons 14 a with one of up spinand down spin flow to the top surface side of the conductive layer 12 aand spin-polarized electrons 14 b with the other flow to the lowersurface side of the conductive layer 12 a. This generates a spin currentthat applies a spin torque to the storage layer 21 of themagnetoresistive element 20 to switch the magnetization direction of thestorage layer 21. Alternatively, a voltage may be applied, in the writeoperation, to the reference layer 23 of the magnetoresistive element 20via a transistor that is not shown, as in a third embodiment that isdescribed later. The applied voltage changes the uniaxial magneticanisotropy of the storage layer 21 in the MTJ element 20 to enable themagnetization of the storage layer 21 to switch easily.

The conductive layers 12 a and 12 b of the magnetic memory according tothe first embodiment include an alloy having a face-centered cubic (fcc)structure. The alloy is at least one selected from Ir—Ta, Ir—V, Au—V,Au—Nb, or Pt—V, or at least two of the above alloys selected andcombined. As used herein, a phrase referring to “at least one of” a listof items refers to any combination of those items, including a singlemember. As an example, “at least one of: a, b, or c” is intended tocover a, b, c, a-b, a-c, b-c, and a-b-c.” The alloy Ir—Ta, for example,means an alloy including Ir and Ta. The expression “IrTa” also means analloy including Ir and Ta.

The material with the fcc structure improves the voltage assistedmagnetic anisotropy control effect, and also the spin Hall angle of theconductive layer. Therefore, if such a material is used to form theconductive layer, and also the storage layer 21 (i.e., if both theconductive layer and the storage layer 21 are formed of a magneticmaterial having the same Δ), the switching current Ic may be reduced ascompared to the case where another material is used for the conductivelayer.

The reduction in switching current is observed for such materials asIr_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The materialsIr_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35) preferablyhave the fcc structure.

As described above, the magnetic memory according to the firstembodiment improves the write efficiency.

(Modification)

A modification of the magnetic memory according to the first embodimentwill be described with reference to FIG. 5.

The magnetic memory according to the modification has the same structureas the magnetic memory according to the first embodiment shown in FIG. 4except that the conductive layer 12 a has a multilayer structureincluding a conductive layer 12 a ₁ and a conductive layer 12 a ₂ (FIG.5). The MTJ element 20 is disposed on the conductive layer 12 a ₁. Likethe first embodiment, if the conductive layer 12 a ₁ includesIr_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), the reductionin switching current is observed. The material may be one ofIr_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from0.05 to 0.35), and Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or two ormore of these alloys that are combined.

A sample is prepared, in which an in-plane magnetization MTJ element 20having a structure CoFeB (2 nm)/MgO (1.5 nm)/CoFeB (1.2 nm)/Co (0.6nm)/Ru (0.9 nm)/CoFe (1.8 nm)/IrMn (8 nm)/Ta (5 nm) is disposed on theconductive layer 12 a having a two-layer structure including a Ta layer12 a ₂ having a thickness of 5 nm and a Ir₉₀Ta₁₀ layer 12 a ₁ having athickness of t nm. The storage layer 21 of the MTJ element 20 is theCoFeB layer having a thickness of 2 nm, the nonmagnetic insulating layer22 is the MgO layer having a thickness of 1.5 nm, and the referencelayer 23 has a multilayer structure including the CoFeB layer having athickness of 1.2 nm, the Co layer having a thickness of 0.6 nm, the Rulayer having a thickness of 0.9 nm, and the CoFe layer having athickness of 1.8 nm. The IrMn layer having a thickness of 8 nm isdisposed on the reference layer 23, and the Ta layer having a thicknessof 5 nm is disposed on the IrMn layer.

FIG. 6 shows the result of measurements of switching current density Jcrelating to an SOT current for switching the magnetization of thestorage layer 21 included in the MTJ element 20 of the sample, when thethickness t (nm) of the Ir₉₀Ta₁₀ layer 12 a ₁ is changed in a range from1 nm to 12 nm. As can be understood from FIG. 6, the switching currentdensity Jc decreases if the thickness t of the Ir₉₀Ta₁₀ layer is greaterthan 3 nm, and further decreases if the thickness is greater than 5 nm.

The decrease in the switching current can also be observed when thematerial of the conductive layer 12 a ₁ is Ir_(1-x)Ta_(x) (x is from0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (xis from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), orPt_(1-x)V_(x) (x is from 0.05 to 0.35). The tendency shown in FIG. 6 mayalso be observed when a material obtained by combining at least two ofthe above alloy is used for the conductive layer 12 a.

The magnetic memory according to the modification also decreases thewrite current and the power consumption. Furthermore, the magneticmemory according to the modification improves the write efficiency, likethe first embodiment.

(Magnetic Material)

The magnetic materials of the storage layer 21 and the reference layer23 in the first embodiment and its modification are not limited, butpreferably at least one selected from Ni—Fe alloy, Co—Fe alloy, Co—Fe—Nialloy, an amorphous material such as (Co, Fe)—(B), (Co, Fe, Ni)—(B),(Co, Fe, Ni)—(B)—(P, Al, Mo, Nb, Mn) or Co—(Zr, Hf, Nb, Ta, Ti), or aHeusler material such as Co—Fe—Al, Co—Fe—Si, Co—Mn—Si, or Co—Mn—Al. Morepreferably, the storage layer 21 and the reference layer 23 have amultilayer structure.

If the memory elements are densely disposed with intervals of 30 nm orless, the storage layer 21 preferably has a multilayer structure.

If the spin of the magnetic layer is parallel to the film plane (forexample, the top surface of the multilayer structure), the multilayerstructure preferably is CoFe(B)/nonmagnetic metal (one of Cu, Ag, andAu)/CoFe(B), Fe(CoB)/Cr/Fe(CoB), Mn-based Heusler alloy/MgO/Mn-basedHeusler alloy, or fcc magnetic layer/nonmagnetic metal (Ru or Ir)/fccmagnetic layer/(Ta, W, Mo)/CoFeB. The expression CoFe(B) means that B(boron) may be included, therefore CoFeB or CoFe. Similarly, Fe(CoB)means Fe or FeCoB. The expression (Ta, W, Mo) means at least one of Ta,W, or Mo is included.

If the spin of the magnetic layer is perpendicular to the film plane,the multilayer structure preferably is Co(Fe)(B)/Pt/Co(Fe)(B),Co(Fe)(B)/Pd/Co(Fe)(B), Co(Fe)(B)/Ni/Co(Fe)(B), (Co/Pt)n/Ru, orIr/(Co/Pt)m (with CoFeB disposed at the interface with the tunnelinsulating layer), or fcc magnetic layer/nonmagnetic metal (Ru orIr)/fcc magnetic layer/(Ta, W, Mo)/CoFeB.

The reference layer 23 preferably has one-directional magneticanisotropy, and the storage layer 21 preferably has uniaxial magneticanisotropy. The thickness of these layers is preferably from 0.1 nm to10 nm. These magnetic layers need to be thick enough not to enter thesuperparamagnetic state, and therefore preferably have a thickness of0.4 nm or more.

The magnetic characteristics of the aforementioned magnetic materialsmay be adjusted by adding thereto a nonmagnetic element such as silver(Ag), copper (Cu), gold (Au), aluminum (Al), magnesium (Mg), silicon(Si), bismuth (Bi), tantalum (Ta), boron (B), carbon (C), oxygen (O),nitrogen (N), palladium (Pd), platinum (Pt), zirconium (Zr), iridium(Ir), tungsten (W), molybdenum (Mo), or niobium (Nb). Other physicalcharacteristics such as crystallinity, the mechanical characteristics,and the chemical characteristics may be adjusted by the addition of thenonmagnetic element.

The magnetic layer that is close to the tunnel insulating layer 22 inMTJ element 20 preferably includes a material having a large magneticresistance (MR) such as Co—Fe, Co—Fe—Ni, or Fe-rich Ni—Fe, and themagnetic layer that is not in contact with the tunnel insulating layerpreferably includes an amorphous material such as Ni-rich Ni—Fe, Ni-richNi—Fe—Co, or CoFeB to curb variations in switching current with thelarge MR being maintained.

The material of the reference layer 23 is not limited as long as themagnetization is stably fixed.

Specifically, the magnetization may be fixed in one direction if themagnetic layer has a three-layer structure such as Co(Co—Fe)/Ru(ruthenium)/Co(Co—Fe), Co(Co—Fe)/Rh (rhodium)/Co(Co—Fe), Co(Co—Fe)/Ir(iridium)/Co(Co—Fe), Co(Co—Fe)/Os (osmium)/Co(Co—Fe), Co(Co—Fe)/Re(rhenium)/Co(Co—Fe), amorphous material layer such as Co—Fe—B/Ru(ruthenium)/Co—Fe, amorphous material layer such as Co—Fe—B/Ir(iridium)/Co—Fe, amorphous material layer such asCo—Fe—B/Os(osmium)/Co—Fe, amorphous material layer such as Co—Fe—B/Re(rhenium)/Co—Fe, (Co/Pt)n/Ru/(Co/Pt)m/CoFeB (n and m each indicate thenumber of stacked layers), (Co/Pt) n/Ir/(Co/Pt)m/CoFeB,(Co/Pt)n/Re/(Co/Pt)m/CoFeB, or (Co/Pt)n/Rh/(Co/Pt)m/CoFeB. Theexpression (Co/Pt)n means that the two-layer structure Co/Pt is stackedn times, and (Co/Pt)m means that the two-layer structure Co/Pt isstacked m times.

An antiferromagnetic layer is preferably disposed near the multilayerstructure. The antiferromagnetic layer may include Fe—Mn, Pt—Mn,Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, or Fe₂O₃. With the aforementionedstructure, the magnetization of the reference layer is stably fixedwithout being influenced by the current magnetic field from a bit lineor a word line.

The stray field from the reference layer may be reduced (or adjusted)and the shift of the magnetization in the storage layer may be adjustedby changing the thickness of the two ferromagnetic layers included inthe reference layer. The magnetic layer (the reference layer) need to bethick enough not to enter the superparamagnetic state, and thereforepreferably have a thickness of 0.4 nm or more.

A nonmagnetic insulating material or a nonmagnetic metal is used to formthe nonmagnetic layer 22 of the magnetoresistive element 20. Thenonmagnetic insulating material is preferably an oxide such as AlOx,MgO, Mg—AlOx, or Mg—ZnOx. The composition does not need to be completelyaccurate from the stoichiometric point of view. For example, oxygen ornitrogen may further be added or removed. The nonmagnetic layer 22 ispreferably as thin as possible to allow the tunneling current to flow.The nonmagnetic metal may be Cu, Ag, or Au.

(Second Embodiment)

A magnetic memory according to a second embodiment will be describedwith reference to FIG. 7. The magnetic memory according to the secondembodiment includes at least one memory cell, which is shown in FIG. 7.The memory cell includes a conductive layer 12, terminals 13 a, 13 b ₁,and 13 b ₂, magnetoresistive elements 20 ₁ and 20 ₂, switches 25 ₁ and25 ₂, and switches 30 ₁ and 30 ₂.

The conductive layer 12 includes the same material as the conductivelayer 12 a of the first embodiment. The conductive layer 12 thusincludes any of Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having theface-centered cubic (fcc) structure, or at least two of the above alloysthat are combined to make an alloy. The conductive layer including sucha material reduces the switching current Ic more than the conductivelayer including a material other than the above materials, as in thecase of the first embodiment. Like the first embodiment, the decrease inthe switching current can be observed when the material of theconductive layer 12 is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4),Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x isfrom 0.05 to 0.35). The materials Ir_(1-x)Ta_(x) (x is from 0.05 to0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x)(x is from 0.05 to 0.35) have the fcc structure.

The terminals 13 a, 13 b ₁, and 13 b ₂ are disposed on the lower surfaceof the conductive layer 12. In FIG. 7, the terminal 13 a is disposedbetween the terminal 13 b ₁ and the terminal 13 b ₂.

The magnetoresistive element 20 ₁ is disposed on the conductive layer 12between the terminal 13 a and the terminal 13 b ₁, and themagnetoresistive element 20 ₂ is disposed on the conductive layer 12between the terminal 13 a and the terminal 13 b ₂. The magnetoresistiveelement 20 _(i) (i=1, 2) includes a storage layer 21 disposed on theconductive layer 12, a nonmagnetic insulating layer 22 disposed on thestorage layer 21, a reference layer 23 disposed on the nonmagnetic layerinsulating layer 22, and a cap layer 24 disposed on the reference layer23. The magnetization direction of the storage layer 21 included in themagnetoresistive element 20 ₁ and the magnetization direction of thestorage layer 21 included in the magnetoresistive element element 20 ₂are opposite to each other.

A switch 25 _(i) is connected to the cap layer 24 of themagnetoresistive element 20 _(i) (i=1, 2). A switch 30 ₁ is connected tothe terminal 13 b ₁, and a switch 30 ₂ is connected to the terminal 13 b₂.

In the magnetic memory having the above-described structure, a writeoperation is performed by applying a voltage to the cap layers 24 of themagnetoresistive elements 20 ₁ and 20 ₂ via the switches 25 ₁ and 25 ₂to change the magnetic anisotropy of the storage layer 21 of each of themagnetoresistive elements 20 ₁ and 20 ₂, and then turning on theswitches 30 ₁ an 30 ₂ to cause a write current I_(w) to flow from theterminal 13 a to the terminal 13 b ₁, and from the terminal 13 a to theterminal 13 b ₂. The direction of the write current flowing from theterminal 13 a to the terminal 13 b ₁ and the direction of the writecurrent flowing from the terminal 13 a to the terminal 13 b ₂ areopposite to each other. Therefore, when a write operation is performed,the spin received by the storage layer of the magnetoresistive element20 ₁ from the conductive layer 12 is opposite to the spin received bythe storage layer of the magnetoresistive element 20 ₂ from theconductive layer 12.

In a read operation, the switches 30 ₁ and 30 ₂ are turned off and theswitches 25 ₁ and 25 ₂ are turned on, a read current is caused to flowfrom the terminal 13 a to the magnetoresistive element 20 ₁ and to themagnetoresistive element 20 ₂, and differential reading is performed byusing outputs from the switches 25 ₁ and 25 ₂. A high-speed readoperation can be performed in this manner.

The magnetic memory according to the second embodiment has a high-speedvoltage control spintronic memory (VoCSM) architecture in which twomagnetoresistive elements serve as one bit. The read operation of thismemory is performed at a high speed by differentially reading datastored in the two magnetoresistive elements, and the write operation isperformed with the magnetic anisotropy of the magnetoresistive elementbeing reduced by a voltage effect to shorten the write time to 1/10 (toimprove the write speed) as compared with a magnetic memory with thesame write current density.

Generally, a memory of differential type requires a current, the amountof which is twice the normally used amount, since the directions ofmagnetization of the storage layers included in the two magnetoresistiveelements need to be switch at a time. If an alloy such as Ir_(1-x)Ta_(x)(x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35),Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or an alloy obtainedby combining at least two of these alloys is used to form the conductivelayer 12 of the second embodiment, the write current density may beconsiderably reduced, and thus a high-speed VoCSM architecture with lowpower consumption may be obtained.

The magnetic memory according to the second embodiment improves thewrite efficiency, like the magnetic memory according to the firstembodiment.

(Modification)

A magnetic memory according to a modification of the second embodimentwill be described with reference to FIG. 8. The magnetic memoryaccording to the modification has a configuration in which theconductive layer 12 of the magnetic memory according to the secondembodiment shown in FIG. 7 has a two-layer structure as in themodification of the first embodiment shown in FIG. 5. The conductivelayer 12 thus has a multilayer structure including a conductive layer 12₁ and a conductive layer 12 ₂ as shown in FIG. 8. The magnetoresistiveelements 20 ₁ and 20 ₂ are disposed on the conductive layer 12 ₁, andthe terminals 13 a, 13 b ₁, and 13 b ₂ are connected to the conductivelayer 12 ₂. The terminals 13 a, 13 b ₁, and 13 b ₂ may be connected tothe conductive layer 12 ₁. As in the first embodiment, a decrease inwrite current is observed if the conductive layer 12 ₁ is Ir_(1-x)Ta_(x)(x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35),Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35). The material may beone of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (xis from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35), or analloy obtained by combining at least two of the above alloys.

A sample is prepared, in which the conductive layer 12 has a two-layerstructure including a Ta layer 12 ₂ having a thickness of 5 nm, and aAu₉₀V₁₀ layer 12 ₁ having a thickness of t nm, and an in-planemagnetization MTJ element having a structure CoFeB (2 nm)/MgO (1.5nm)/CoFeB (1.2 nm)/Co (0.6 nm)/Ru (0.9 nm)/CoFe (1.8 nm)/IrMn (8nm)/Ta(5 nm) is disposed on the layer 12 ₁. The storage layer 21 is aCoFeB layer having a thickness of 2 nm, the nonmagnetic insulating layer22 is a MgO layer having a thickness of 1.5 nm, and the reference layer23 has a multilayer structure including a CoFeB layer having a thicknessof 1.2 nm, a Co layer having a thickness of 0.6 nm, a Ru layer having athickness of 0.9 nm, and a CoFe layer having a thickness of 1.8 nm. AnIrMn layer having a thickness of 8 nm is disposed on the reference layer23, and a Ta layer having a thickness of 5 nm is disposed on the IrMnlayer.

FIG. 9 shows the result of measurements of switching current density Jcrelating to an SOT current for switching the magnetization of thestorage layer 21 included in the magnetoresistive element 20 of thesample, when the thickness t (nm) of the Au₉₀V₁₀ layer 12 ₁ is changedin a range from 1 nm to 12 nm. As can be understood from FIG. 9, theswitching current density Jc decreases if the thickness t of the Au₉₀V₁₀layer is greater than 3 nm, and further decreases if the thickness isgreater than 5 nm.

The decrease in the switching current can also be observed when thematerial of the conductive layer 12 ₁ is Ir_(1-x)Ta_(x) (x is from 0.05to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x isfrom 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), orPt_(1-x)V_(x) (x is from 0.05 to 0.35). The tendency shown in FIG. 9 mayalso be observed when a material obtained by combining at least two ofthe above alloys is used for the conductive layer 12 ₁.

The magnetic memory according to the modification also decreases thewrite current and the power consumption. Furthermore, the magneticmemory according to the modification improves the write efficiency, likethe second embodiment.

The magnetic material of the storage layer 21 and the reference layer 23in the second embodiment and its modification is not limited, butpreferably at least one selected from Ni—Fe alloy, Co—Fe alloy, Co—Fe—Nialloy, an amorphous material such as (Co, Fe)—(B), (Co, Fe, Ni)—(B),(Co, Fe, Ni)—(B)—(P, Al, Mo, Nb, Mn) or Co—(Zr, Hf, Nb, Ta, Ti), or aHeusler material such as Co—Fe—Al, Co—Fe—Si, Co—Mn—Si, or Co—Mn—Al. Morepreferably, the storage layer 21 and the reference layer 23 have amultilayer structure.

If the memory elements are densely disposed with intervals of 30 nm orless, the storage layer 21 preferably has a multilayer structure.

If this multilayer structure is used for a magnetic memory according toa third embodiment, which is described below, the margin for preventingerroneous writing is increased by applying a voltage to magnetoresistiveelements serving as a plurality of bits disposed on an SO layer, causinga current to flow through the SO layer, and switching the magnetizationof only the storage layers of the magnetoresistive elements to which thevoltage is applied. The margin can be further increased by changing thesign of voltage applied to the magnetoresistive elements, and switchingthe magnetization of the storage layers included in the magnetoresistiveelements to which the negative voltage is applied. If the storage layershave a multilayer structure described above, the margin is increasedfurther.

(Third Embodiment)

A magnetic memory according to the third embodiment is shown in FIG. 10.The magnetic memory according to the third embodiment is described withreference to FIGS. 10 to 12. The magnetic memory according to thisembodiment includes at least one memory cell, the configuration of whichis shown in FIG. 10.

The memory cell 10 includes a conductive layer 12, a plurality (forexample eight) of magnetoresistive elements 20 ₁ to 20 ₈ disposed on onesurface of the conductive layer 12 to be separate from one another,transistors 25 _(i) each corresponding to one of the magnetoresistiveelements 20 _(i) (i=1, . . . , 8), transistors 30 and 31 for causing acurrent to flow through the conductive layer 12, and control circuits110 and 120.

The material of the conductive layer 12 is any of Ir—Ta, Ir—V, Au—V,Au—Nb, and Pt—V having the face-centered cubic (fcc) structure, or analloy obtained by combining at least two of these alloys. Like the firstembodiment, the use of such a material to form the conductive layer maylead to a decrease in the switching current Ic as compared to the casewhere a material other than the above materials is used for theconductive layer.

Like the first embodiment, the decrease in the switching current can beobserved if the material of the conductive layer is Ir_(1-x)Ta_(x) (x isfrom 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x)(x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), orPt_(1-x)V_(x) (x is from 0.05 to 0.35). Each of Ir_(1-x)Ta_(x) (x isfrom 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x)(x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), andPt_(1-x)V_(x) (x is from 0.05 to 0.35) has the fcc structure. The writecurrent I_(w) flows through the conductive layer 12.

The direction of current flowing through the conductive layer 12 iscontrolled by the control circuit 110. When the current flows, electrons14 a with up spin and electrons 14 b with down spin flow through theconductive layer 12. The directions of the spins of the electrons 14 aand 14 b are indicated by arrows.

Each magnetoresistive element 20 _(i) (1=1, . . . , 8) has a multilayerstructure including a storage layer 21 disposed on the conductive layer12, a nonmagnetic layer 22 disposed on the storage layer 21, and thereference layer 23 disposed on the nonmagnetic layer 22. Themagnetoresistive element 20 _(i) (i=1, . . . , 8) may be either amagnetic tunnel junction (MTJ) element in which the nonmagnetic layer 22is an insulating layer, or a giant magneto-resistive (GMR) element inwhich the nonmagnetic layer 22 is a nonmagnetic metal layer. If themagnetoresistive element is an MTJ element of in-plane magnetizationtype, in which the magnetization directions of the storage layer 21 andthe reference layer 23 are parallel to the film plane, and perpendicularto the layer-stacking direction of the multilayer structure, a CoFeBlayer, for example, is used as the storage layer 21, a MgO layer, forexample, is used as the nonmagnetic layer 22, and a syntheticantiferromagnetic multilayer structure is used as the reference layer,which includes, for example, a CoFeB layer, a Ru layer disposed on theCoFeB layer, and a CoFe layer disposed on the Ru layer, the CoFeB layerand the CoFe layer being coupled by antiferromagnetic coupling via theRu layer. In the in-plane magnetization MTJ element, anantiferromagnetic layer of IrMn, for example, is disposed on thereference layer 23 in order to fix the magnetization of the referencelayer 23. Although the magnetoresistive elements 20 ₁ to 20 ₈ aredisposed on the conductive layer 12 in FIG. 10, they may be disposedunder the conductive layer 12.

The MTJ element is patterned to have a rectangular shape. The stablemagnetization direction in the storage layer and the reference layer isalong the long axes of these layers due to the shape magneticanisotropy. The stable magnetization direction is indicated by arrows inFIG. 10. The stability is called “(long axis) uniaxial magneticanisotropy.” The uniaxial magnetic anisotropy is dependent on the aspectratio of the rectangle, the thickness of the storage layer, and themagnetization of the magnetic layer, and the write current thresholdvalue I_(co), which is described later, is proportional to the uniaxialmagnetic anisotropy. Each magnetoresistive element 20 _(i) (i=1, . . . ,8) is a 1-bit storage element, and the memory cell 10 is, for example, a1-byte cell including 8 bits.

One (first terminal) of the source and the drain of each transistor 25_(i) (i=1, . . . , 8) is electrically connected to the reference layer23 of the corresponding magnetoresistive element 20 _(i), the other(second terminal) is connected to a selection line (not shown) forselecting the memory cell, and the gate (control terminal) is connectedto a selection line (not shown) for selecting the correspondingmagnetoresistive element 20 _(i). Therefore, each transistor 25 _(i)(i=1, . . . , 8) is also called a bit selection transistor for selectingthe corresponding magnetoresistive element 20 _(i). Eachmagnetoresistive element 20 _(i) (i=1, . . . , 8) has a first terminaland a second terminal, the first terminal being connected to theconductive layer 12, and the second terminal being connected to thefirst terminal of the bit selection transistor 25 _(i). The gate(control terminal) and the second terminal of each of the bit selectiontransistors 25 ₁ to 25 ₈ is connected to the control circuit 120 so thatthe ON state and the OFF state of each bit selection transistor iscontrolled by the control circuit 120 and the potential applied to thesecond terminal of each of the magnetoresistive elements 20 ₁ to 20 ₈ iscontrolled.

One (first terminal) of the source and the drain of the transistor 30 isconnected to the terminal 13 a, which is one of the two terminals 13 aand 13 b of the conductive layer 12, the other (second terminal) isconnected to a power supply or a current source, and the gate (controlterminal) receives a signal for selecting the memory cell 10. One (firstterminal) of the source and the drain of the transistor 31 is connectedto the terminal 13 b, which is the other of the two terminals 13 a and13 b of the conductive layer 12, the other (second terminal) isconnected to a power supply or a current source, and the gate (controlterminal) receives a signal for selecting the memory cell 10. A writeoperation to write data to the storage layer 21 of each magnetoresistiveelement 20 _(i) (1=1, . . . , 8) is performed by causing a write currentto flow between the transistors 30 and 31 through the conductive layer12. The transistors 30 and 31 are also called “byte selectiontransistors.” The gate of each of the byte selection transistors 30 and31 is connected to the control circuit 110 so that the ON state and theOFF state of the byte selection transistors 30 and 31 are controlled.The direction of the current flowing through the conductive layer 12 isalso controlled by the control circuit 110. The transistor 31 may beeliminated, and the second terminal 13 b of the conductive layer 12 maybe grounded.

In the following descriptions, each magnetoresistive element 20 _(i)(i=1, . . . , 8) is assumed to be an MTJ element. The nonmagnetic layer22 of each MTJ element, which is a MgO layer for example, is thickenough (for example, about 2 nm) to restrict the tunneling currentflowing through the nonmagnetic layer 22 to be 1 μA or less. Therefore,when the control circuit 120 turns on the bit selection transistor 25_(i) (i=1, . . . , 8), a voltage of about 0.5 V may be applied to thestorage layer 21.

When the voltage is applied to the storage layer of the MTJ element,perpendicular magnetic anisotropy is induced to provide a verticalcomponent to the magnetization of the storage layer. As a result, thestability of the magnetization (uniaxial magnetic anisotropy) isweakened. Thus, when the bit selection transistor 25 _(i) (i=1, . . . ,8) is in the ON state, the write current threshold value I_(co) of thecorresponding bit can be reduced. This state is called “bithalf-selection state,” and the write current threshold value in thisstate is set to be I_(ch). In this embodiment, parameters of the layerssuch as the storage layer 21 are set so that the following formula, forexample, holds:I _(ch) ≈I _(co)/2  (1)

The conductive layer 12 includes a material having a large spin Halleffect or a large Rashba effect that provides the spin orbit couplingfunction. The conductive layer 12 is disposed under the MTJ element andelectrically connecting adjacent MTJ elements in series. Typically, MTJelements of 1 byte (eight) are connected in series. The thickness of theconductive layer 12 is generally about 10 nm, and the sheet resistanceof the conductive layer 12 is as low as about 1000Ω. This allows theeight (1 byte) MTJ elements to be connected in series. The seriesresistance of the MTJ elements is about 10 kΩ, which is substantiallythe same as that of a minute transistor. Therefore, a required writecurrent may be provided.

When the byte selection transistors 30 and 31 are turned on by thecontrol circuit 110, a write current I_(w) flows through the conductivelayer 12. In the memory cell 10 shown in FIG. 10, spin-polarizedelectrons with spin directed from the near side to the far side in thedrawing are accumulated around the top surface of the conductive layer12, and spin-polarized electrons 13 a, 13 b with spin directed from thefar side to the near side in the drawing are accumulated near the lowersurface of the conductive layer 12 due to the electron scattering causedby the spin orbit coupling in the conductive layer 12.

When a bit is selected in the memory cell 10 having the above-describedconfiguration, data may be written to the bit due to the spin transfertorque caused by the accumulated spin-polarized electrons and themagnetization of the storage layer 21 when the write current I_(W)exceeds the threshold current I_(c0).

Similarly, when a bit is half-selected, data may be written to the bitdue to the spin transfer torque caused by the accumulated spin-polarizedelectrons and the magnetization of the storage layer 21 when the writecurrent I_(w) exceeds the threshold current I_(c0)/2.

(Write Method)

A method of writing data to the memory cell 10 shown in FIG. 10 will bedescribed below with reference to FIGS. 11 and 12. In this embodiment, atwo-stage write operation is performed on the memory cell 10. FIGS. 11and 12 show a case where 1-byte data (0, 1, 1, 0, 0, 0, 0, 1) is writtento the memory cell 10.

First, as shown in FIG. 11, the byte selection transistors 30 and 31 andthe bit selection transistors 25 ₁ to 25 ₈ are turned on by means of thecontrol circuit 110 and the control circuit 120, and a first potential(for example, a positive potential) is applied to the reference layers23 of the MTJ elements 20 ₁ to 20 ₈, and a write current I_(w) is causedto flow between the first terminal 13 a and the second terminal 13 b ofthe conductive layer 12. At this time, the magnetization stability(uniaxial magnetic anisotropy) of the storage layers 21 in all of theMTJ elements 20 ₁ to 20 ₈ is weakened, and therefore the thresholdcurrent of the storage layers 21 is changed from I_(c0) to I_(ch), anddata “0” is written to all of the MTJ elements 20 ₁ to 20 ₈, like (0, 0,0, 0, 0, 0, 0, 0), by a write current I_(w0) (I_(w)>I_(w0)>I_(ch)). Thewrite error rate may be reduced to about 10⁻¹¹ if the write current isabout 1.5 times the threshold current. Therefore, the following formulaholds:I _(w0)≈1.5I _(ch)  (2)

Next, the bit selection transistors connected to bits to which “1” is tobe written, for example the bit selection transistors 25 ₂, 25 ₃, and 25₈, are turned on by means of the control circuit 120, and a secondpotential (for example a negative potential) is applied to the referencelayers 23 of the MTJ elements 20 ₂, 20 ₃, and 20 ₈. A positive potentialis preferably applied to the other MTJ elements 20 ₁, 20 ₄, 20 ₅, 20 ₆,and 20 ₇ to reduce the error rate. The byte selection transistors 30 and31 are also turned on by means of the control circuit 110 to cause awrite current I_(w1) (I_(c0)>I_(w1)>I_(ch)) to flow through theconductive layer 12 in a direction opposite to the direction for writingthe data “0.” As a result, data “1” is written to the storage layer 21of each of the MTJ elements 20 ₂, 20 ₃, and 25 ₈ (FIG. 12). At thistime, the formula holds, as in the aforementioned case:I _(w1)≈1.5I _(ch)  (3)

Thus, 1-byte data (0, 1, 1, 0, 0, 0, 0, 1) can be written by thetwo-stage write operation. The two-stage write operation is madepossible by the cooperation of the control circuit 110 and the controlcircuit 120. A first write circuit used in the first-stage writeoperation and a second write circuit used in the second-stage writeoperation in the two-stage write operation are connected to the controlcircuit 110 and the control circuit 120.

A read operation is performed in the following manner. When data is readfrom the memory cell 10, the byte selection transistors 30 and 31 andthe bit selection transistors 25 ₁ to 25 ₈ of the memory cell 10 areturned on to select bits from which data is read. The resistance of eachof the selected bits is measured using a current flowing between theselection transistor connected to the selected bit and one of the byteselection transistors, and type of data is determined based on themeasured resistance.

In the foregoing and the following embodiments, MTJ elements within-plane magnetization are described. However, the magnetoresistiveelements are not limited to this type, but MTJ elements withperpendicular magnetization, for example, may also be used. As in thecase of the MTJ elements with in-plane magnetization, the bit selectiontransistors are turned on, and bits are selected by decreasing orincreasing the write threshold current.

As described above, in the memory cell according to the thirdembodiment, an alloy having the face-centered cubic (fcc) structure suchas Ir—Ta, Ir—V, Au—V, Au—Nb, or Pt—V, or an alloy obtained by two ormore of the above alloys is used as the material of the conductive layer12. By using such a material to form the conductive layer, the switchingcurrent Ic may be decreased as compared to the case where a materialother than the above-described materials are used to form the conductivelayer, as in the case of the first embodiment.

FIG. 13 shows a result of measurements of the current density Jsw, atwhich the magnetization of the storage layer is switched, when a writeoperation is performed by applying a voltage to the reference layer ofone of the magnetoresistive elements included in the memory cell 10according to the third embodiment (VoCSM), and when a write operation isperformed only by causing a current to flow through the conductive layer12 without applying a voltage to the MTJ element. As can be understoodfrom FIG. 13, the write speed in the case where the magnetic anisotropyof the magnetoresistive element is reduced by the voltage (VoCSM) ishigher than the write speed in the write operation using the spin Halleffect, when the write current density is the same.

A voltage may be applied to the reference layer of the magnetoresistiveelement also in the first embodiment, the second embodiment, and theirmodifications.

The magnetic memory according to the third embodiment improves the writeefficiency, like the magnetic memory according to the first embodiment.

(Modification)

A magnetic memory according to a modification of the third embodimentwill be described below. The magnetic memory according to themodification has a structure in which the conductive layer 12 of themagnetic memory according to the third embodiment shown in FIG. 10 hastwo layers, like the modification of the first embodiment shown in FIG.5. The conductive layer 12 has a multilayer structure including a firstconductive layer and a second conductive layer, and the magnetoresistiveelements 20 ₁ to 20 ₈ are disposed on the first conductive layer. Thematerial of the first conductive layer is the same as the conductivelayer 12, i.e., any of Ir—Ta, Ir—V, Au—V, Au—Nb or Pt—V having the fccstructure, or an alloy obtained by combining at least two of the abovealloys. The material of the second conductive layer is a well-knownSO-layer material such as Ta or W.

In the modification, the conductive layer 12 has a two-layer structureincluding a Ta layer having a thickness of 5 nm and a Pt₉₀V₁₀ layerhaving a thickness of t nm. An MTJ element with in-plane magnetizationis formed on the conductive layer, the MTJ element having a multilayerstructure expressed as CoFeB (2 nm)/MgO (1.5 nm)/CoFeB (1.2 nm)/Co (0.6nm)/Ru (0.9 nm)/CoFe (1.2 nm)/IrMn (8 nm)/Ta (5 nm). Thus, the MTJelement has a multilayer structure including a CoFeB layer having athickness of 2 nm, an MgO layer having a thickness of 1.5 nm, a CoFeBlayer having a thickness of 1.2 nm, a Co layer having a thickness of 0.6nm, a Ru layer having a thickness of 0.9 nm, a CoFe layer having athickness of 1.8 nm, a IrMn layer having a thickness of 8 nm, and a Talayer having a thickness of 5 nm, the layers being stacked in thisorder. A sample is prepared, in which an MTJ element with perpendicularmagnetization having a multilayer structure expressed as (Co (0.4 nm)/Pt(0.4 nm))n/CoFeB (1.0 nm)/MgO (1.5 nm)/CoFeB (1.0 nm)/Ta (0.5 nm)/(Co(0.4 nm)/Pt (0.6 nm))m/Ir (0.5 nm)/(Co (0.4 nm)/Pt (0.6 nm))k is formedon the same conductive layer. FIG. 14 shows a result of measurements ofthe switching current density Jc relating to the SOT current for the MTJelements with in-plane magnetization and the MTJ element withperpendicular magnetization when the thickness t of the Pt₉₀V₁₀ layer inthe conductive layer is changed to 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7nm, 8 nm, 9 nm, 10 nm, and nm. In the measurements of the MTJ elementwith perpendicular magnetization, an in-plane magnetic field H_(ex)=100Oe is applied to perform the switching by using the SOT.

A voltage of 1 V is applied to the MTJ elements of both types in orderto reduce the switching current by the voltage controlled magneticanisotropy effect. As can be understood from FIG. 14, the switchingcurrent Jc decreases when the thickness t is 3 nm or more, morepreferably 5 nm or more.

The decrease in the switching current is also observed when the materialof the first conductive layer is Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4),Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x isfrom 0.05 to 0.35). A material obtained by combining at least two of theabove alloys may also be used to form the first conductive layer to havea similar effect to FIG. 14.

The magnetic memory according to the modification reduces the writecurrent and the power consumption. Furthermore, the magnetic memoryaccording to the modification improves the write efficiency, like themagnetic memory according to the third embodiment.

(Fourth Embodiment)

A magnetic memory according to a fourth embodiment will be describedbelow with reference to FIG. 15. As shown in FIG. 15, the magneticmemory according to the fourth embodiment includes memory cells 10 ₀₀,10 ₀₁, 10 ₁₀, and 10 ₁₁, word lines WL₀₀ and WL₁₀, bit lines BL₀₀ toBL₇₀ and BL₀₁ to BL₇₁, write bit lines WBL₀ and WBL₁, and source linesSL₀ and SL₁.

Each memory cell 10 _(ij) (i, j=0, 1) includes a nonmagnetic conductivelayer 12, memory elements (magnetoresistive elements) 20 ₀ to 20 ₇disposed on the conductive layer 12, selection transistors 25 ₀ to 25 ₇,and a selection transistor 30. Each conductive layer 12 has a firstterminal 13 a and a second terminal 13 b. Like the magnetic memory 10according to the first embodiment shown in FIG. 4, each memory element20 _(j) (j=0 . . . , 7) has a multilayer structure including a storagelayer 21, a nonmagnetic layer 22, and a reference layer 23.

The magnetic memory according to the fourth embodiment has first tofourth levels 400, 410, 420, and 430.

In the first level 400, the selection transistors 25 ₀ to 25 ₇ and theselection transistor 30 of each memory cell 10 _(ij) (i, j=0, 1), theword lines WL₀₀ and WL₁₀, the write bit lines WBL₀ and WBL₁, and the bitlines BL₀₀ to BL₇₁ are disposed.

In the second level 410, vias and wiring lines connecting to the firstlevel 400, and the memory elements 20 ₀ to 20 ₇ and the conductive layer12 of each memory cell 10 _(0j) (j=0, 1) are disposed. The solid line411 indicates a region including the memory elements 20 ₀ to 20 ₇ andthe conductive layers 12 of the memory cells 10 ₀₀ and 10 ₀₁.

In the third level 420, vias and wiring lines connecting to the secondlevel 410 and the fourth level 430 and source lines SL₀ and SL₁ aredisposed.

In the fourth level 430, vias and wiring lines connecting to the thirdlevel 420, and the memory elements 20 ₀ to 20 ₇ and the conductive layer12 of each the memory cell 10 _(1j) (j=0, 1) are disposed. The solidline 431 indicates a region including the memory elements 20 ₀ to 20 ₇and the conductive layers 12 of the memory cells 10 ₁₀ and 10 ₁₁.

The selection transistors 25 ₀ to 25 ₇, the selection transistors 30,the word lines WL₀₀ and WL₁₀, the bit lines BL₀₀ to BL₇₀ and BL₀₁ toBL₇₁, and the write bit lines WBL₀ and WBL₁ are disposed in the firstlevel 400.

The memory cells 10 ₀₀ and 10 ₀₁ are disposed in the second level 410.The source lines SL₀ and SL₁ are disposed in the third level 420. Thememory cells 10 ₁₀ and 10 ₁₁ are disposed in the fourth level 430.

In each of the memory cells 10 ₀₀ and 10 ₁₀, the reference layer of thememory element 20 _(j) (j=0, . . . , 7) is connected to one of thesource and the drain of the selection transistor 25 _(j), and the otherof the source and the drain of the selection transistor 25 _(j) isconnected to the bit line BL_(j0).

In each of the memory cells 10 ₀₁ and 10 ₁₁, the reference layer of thememory element 20 _(j) (j=0, . . . , 7) is connected to one of thesource and the drain of the selection transistor 25 _(j), and the otherof the source and the drain of the selection transistor 25 _(j) isconnected to the bit line BL_(j1).

In each of the memory cells 10 ₀₀ and 10 ₁₀, the first terminal 13 a isconnected to one of the source and the drain of the selection transistor30, and the other of the source and the drain of the selectiontransistor 30 is connected to the write bit line WBL₀. The secondterminal 13 b is connected to the source line SL₀.

In each of the memory cells 10 ₀₁ and 10 ₁₁, the first terminal 13 a isconnected to one of the source and the drain of the selection transistor30, and the other of the source and the drain of the selectiontransistor 30 is connected to the write bit line WBL₁. The secondterminal 13 b is connected to the source line SL₁.

The write operation and the read operation performed on each memory cell10 _(ij) (i, j=0, 1) of the fourth embodiment having the above-describedconfiguration are the same as those for the magnetic memory according tothe third embodiment.

The material of each conductive layer 12 of the fourth embodiment is anyof Ir—Ta, Ir—V, Au—V, Au—Nb, and Pt—V having the face-centered cubic(fcc) structure, or an alloy obtained by combining at least two of theabove alloys. The conductive layer formed of any of the above-describedmaterials may reduce the switching current Ic as compared to theconductive layer formed of a material other than the above-describedmaterials, when the material of the storage layer 21 is the same (hasthe same Δ).

The reduction in the switching current may also be observed when thematerial is any of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x)(x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5),Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x) (x is from0.05 to 0.35). Each of the materials Ir_(1-x)Ta_(x) (x is from 0.05 to0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), and Pt_(1-x)V_(x)(x is from 0.05 to 0.35) has the fcc structure.

As described above, the magnetic memory according to the fourthembodiment can improve the write efficiency, like the magnetic memoryaccording to the third embodiment.

(Modification)

A magnetic memory according to a modification of the fourth embodimenthas a configuration in which each of the conductive layers 12 in themagnetic memory according to the fourth embodiment has a multilayerstructure including a first conductive layer and a second conductivelayer, and the magnetoresistive elements 20 ₀ to 20 ₇ are disposed onthe first conductive layer, like the modification of the thirdembodiment. The material of the first conductive layer is the same asthat of the conductive layer 12, i.e., any of Ir—Ta, Ir—V, Au—V, Au—Nb,and Pt—V having the fcc structure, or an alloy obtained by combining atleast two of the above alloys. The material of the second conductivelayer is a well-known SO-layer material such as Ta or W.

The magnetic memory according to the modification improves the writeefficiency, like the magnetic memory according to the fourth embodiment.

If the magnetoresistive elements are MTJ elements in the first to fourthembodiments and their modifications, the coercive force of themagnetization free layer in each MTJ element needs to be changed by avoltage. Therefore, it is undesirable that the nonmagnetic insulatinglayer 22 of each MTJ element has a very low resistance area product(RA). A preferable RA is several ten Ω² to several thousand KΩμm². Inthis case, if the resistance is several thousand KΩμm², the switching ina write operation is mainly caused by a voltage and SOT, and if theresistance is several ten Ωμm², the switching is mainly caused by avoltage, SOT, and STT.

The embodiments of the present invention have been described withreference to the specific examples. However, the present invention isnot limited to the specific examples. For example, specific materials,thicknesses, and shapes, of dimensions of the SO layer, and theferromagnetic material layers, insulating films, antiferromagneticmaterial layers, nonmagnetic metal layers, and electrodes that serve asthe ferromagnetic tunnel junction elements, may be arbitrarily selectedby those skilled in the art to carry out the present invention to havesimilar effects. Such elements and layers are also included in the scopeof the present invention.

Similarly, the structure, the material, the shape, and the dimensions ofeach element included in the magnetic memory according to an embodimentof the present invention may be arbitrarily selected by those skilled inthe art to carry out the present invention to have similar effects. Suchelements are included in the scope of the present invention.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and systems describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

The invention claimed is:
 1. A magnetic memory comprising: a firstterminal, a second terminal, and a third terminal; a nonmagneticconductive layer including a first region, a second region, and a thirdregion, the second region being disposed between the first region andthe third region, the first region being electrically connected to thefirst terminal, and the third region being electrically connected to thesecond terminal; and a magnetoresistive element disposed to correspondto the second region, including a first magnetic layer electricallyconnected to the third terminal, a second magnetic layer disposedbetween the first magnetic layer and the second region, and anonmagnetic layer disposed between the first magnetic layer and thesecond magnetic layer, the nonmagnetic conductive layer including atleast one of an alloy including Ir and Ta, an alloy including Ir and V,an alloy including Au and V, an alloy including Au and Nb, or an alloyincluding Pt and V, each of the alloys having an fcc structure.
 2. Themagnetic memory according to claim 1, wherein the second region of thenonmagnetic conductive layer includes a first layer and a second layer,the first layer being disposed between the magnetoresistive element andthe second layer, the first layer including at least one of the alloysand having a thickness of 3 nm or more.
 3. The magnetic memory accordingto claim 1, wherein the nonmagnetic conductive layer includes at leastone of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (xis from 0.05 to 0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 4. Themagnetic memory according to claim 1, wherein the nonmagnetic conductivelayer includes a first layer and a second layer, the first layer beingdisposed on a side of the magnetoresistive element, the first layerincluding at least one of the alloys and having a thickness of 3 nm ormore.
 5. A magnetic memory comprising: a first terminal, a secondterminal, a third terminal, a fourth terminal, and a fifth terminal; anonmagnetic conductive layer including a first region, a second region,a third region, a fourth region, and a fifth region, the second regionbeing disposed between the first region and the fifth region, the thirdregion being disposed between the second region and the fifth region,the fourth region being disposed between the third region and the fifthregion, the first region being electrically connected to the firstterminal, the fifth region being electrically connected to the secondterminal, and the third region being electrically connected to the thirdterminal; a first magnetoresistive element disposed to correspond to thesecond region, including a first magnetic layer electrically connectedto the fourth terminal, a second magnetic layer disposed between thefirst magnetic layer and the second region, and a first nonmagneticlayer disposed between the first magnetic layer and the second magneticlayer; and a second magnetoresistive element disposed to correspond tothe fourth region, including a third magnetic layer electricallyconnected to the fifth terminal, a fourth magnetic layer disposedbetween the third magnetic layer and the fourth region, and a secondnonmagnetic layer disposed between the third magnetic layer and thefourth magnetic layer, the nonmagnetic conductive layer including atleast one of an alloy including Ir and Ta, an alloy including Ir and V,an alloy including Au and V, an alloy including Au and Nb, or an alloyincluding Pt and V, each of the alloys having an fcc structure.
 6. Themagnetic memory according to claim 5, wherein the second region of thenonmagnetic conductive layer includes a first layer and a second layerand the fourth region includes a third layer and a fourth layer, thefirst layer being disposed between the second magnetic layer and thesecond layer, the first layer including at least one of the alloys andhaving a thickness of 3 nm or more, the third layer being disposedbetween the fourth magnetic layer and the fourth layer, and the thirdlayer including at least one of the alloys and having a thickness of 3nm or more.
 7. The magnetic memory according to claim 5, wherein thenonmagnetic conductive layer includes at least one of Ir_(1-x)Ta_(x) (xis from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35),Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 8. The magnetic memoryaccording to claim 5, wherein the nonmagnetic conductive layer includesa first layer and a second layer, the first layer being disposed on aside of the first and second magnetoresistive elements, the first layerincluding at least one of the alloys and having a thickness of 3 nm ormore.
 9. A magnetic memory comprising: a first terminal, a secondterminal, a third terminal, and a fourth terminal; a nonmagneticconductive layer including a first region, a second region, a thirdregion, and a fourth region, the second region being disposed betweenthe first region and the fourth region, the third region being disposedbetween the second region and the fourth region, the first region beingelectrically connected to the first terminal, and the fourth regionbeing electrically connected to the second terminal; a firstmagnetoresistive element disposed to correspond to the second region,including a first magnetic layer electrically connected to the thirdterminal, a second magnetic layer disposed between the first magneticlayer and the second region, and a first nonmagnetic layer disposedbetween the first magnetic layer and the second magnetic layer; and asecond magnetoresistive element disposed to correspond to the thirdregion, including a third magnetic layer electrically connected to thefourth terminal, a fourth magnetic layer disposed between the thirdmagnetic layer and the third region, and a second nonmagnetic layerdisposed between the third magnetic layer and the fourth magnetic layer,the nonmagnetic conductive layer including at least one of an alloyincluding Ir and Ta, an alloy including Ir and V, an alloy including Auand V, an alloy including Au and Nb, or an alloy including Pt and V,each of the alloys having an fcc structure.
 10. The magnetic memoryaccording to claim 9, wherein the second region of the nonmagneticconductive layer includes a first layer and a second layer, and thethird region includes a third layer and a fourth layer, the first layerbeing disposed between the second magnetic layer and the second layer,the first layer including at least one of the alloys and having athickness of 3 nm or more, the third layer being disposed between thefourth magnetic layer and the fourth layer, and the third layerincluding at least one of the alloys and having a thickness of 3 nm ormore.
 11. The magnetic memory according to claim 9, wherein thenonmagnetic conductive layer includes at least one of Ir_(1-x)Ta_(x) (xis from 0.05 to 0.4), Ir_(1-x)V_(x) (x is from 0.05 to 0.35),Au_(1-x)V_(x) (x is from 0.05 to 0.5), Au_(1-x)Nb_(x) (x is from 0.05 to0.35), or Pt_(1-x)V_(x) (x is from 0.05 to 0.35).
 12. The magneticmemory according to claim 9, wherein the nonmagnetic conductive layerincludes a first layer and a second layer, the first layer beingdisposed on a side of the first and second magnetoresistive elements,the first layer including at least one of the alloys and having athickness of 3 nm or more.
 13. A magnetic memory comprising: a firstwiring, a second wiring, a third wiring, a fourth wiring, and a fifthwiring; a first terminal, a second terminal electrically connected tothe fifth wiring, a third terminal, and a fourth terminal electricallyconnected to the fifth wiring; a first conductive layer including afirst region, a second region, and a third region, the second regionbeing disposed between the first region and the third region, the firstregion being electrically connected to the first terminal, and the thirdregion being electrically connected to the second terminal; a secondconductive layer including a fourth region, a fifth region, and a sixthregion, the fifth region being disposed between the fourth region andthe sixth region, the fourth region being electrically connected to thethird terminal, and the sixth region being electrically connected to thefourth terminal; a first magnetoresistive element disposed to correspondto the second region, including a first magnetic layer, a secondmagnetic layer disposed between the first magnetic layer and the secondregion, and a first nonmagnetic layer disposed between the firstmagnetic layer and the second magnetic layer; a second magnetoresistiveelement disposed to correspond to the fifth region, including a thirdmagnetic layer, a fourth magnetic layer disposed between the thirdmagnetic layer and the fifth region, and a second nonmagnetic layerdisposed between the third magnetic layer and the fourth magnetic layer;a first transistor including a fifth terminal electrically connected tothe first magnetic layer, a six terminal electrically connected to thethird wiring, and a first control terminal electrically connected to thefirst wiring; a second transistor including a seventh terminalelectrically connected to the first terminal, an eighth terminalelectrically connected to the second wiring, and a second controlterminal electrically connected to the first wiring; a third transistorincluding a ninth terminal electrically connected to the third magneticlayer, a tenth terminal electrically connected to the third wiring, anda third control terminal electrically connected to the fourth wiring;and a fourth transistor including an eleventh terminal electricallyconnected to the third terminal, a twelfth terminal electricallyconnected to the second wiring, and a fourth control terminalelectrically connected to the fourth wiring, the first wiring, thesecond wiring, the third wiring, and the fourth wiring, and the firsttransistor, the second transistor, the third transistor, and the fourthtransistor being disposed in a first level, the first conductive layerand the first magnetoresistive element being disposed in a second levelthat is above the first level, the fifth wiring being disposed in athird level that is above the second level, and the second conductivelayer and the second magnetoresistive element being disposed in a fourthlevel that is above the third level, and the first conductive layer andthe second conductive layer including at least one of an alloy includingIr and Ta, an alloy including Ir and V, an alloy including Au and V, analloy including Au and Nb, or an alloy including Pt and V, each of thealloys having an fcc structure.
 14. The magnetic memory according toclaim 13, wherein: the second region of the first conductive layerincludes a first layer and a second layer, the first layer beingdisposed between the second magnetic layer and the second layer, thefirst layer including at least one of the alloys and having a thicknessof 3 nm or more; and the fifth region of the second conductive layerincludes a third layer and a fourth layer, the third layer beingdisposed between the fourth magnetic layer and the fourth layer, thethird layer including at least one of the alloys and having a thicknessof 3 nm or more.
 15. The magnetic memory according to claim 13, whereinthe first magnetoresistive element is disposed above the firstconductive layer, and the second magnetoresistive element is disposedabove the second conductive layer.
 16. The magnetic memory according toclaim 13, wherein the first conductive layer and the second conductivelayer include at least one of Ir_(1-x)Ta_(x) (x is from 0.05 to 0.4),Ir_(1-x)V_(x) (x is from 0.05 to 0.35), Au_(1-x)V_(x) (x is from 0.05 to0.5), Au_(1-x)Nb_(x) (x is from 0.05 to 0.35), or Pt_(1-x)V_(x) (x isfrom 0.05 to 0.35).
 17. The magnetic memory according to claim 13,wherein: the first conductive layer includes a first layer and a secondlayer, the first layer being disposed on a side of the firstmagnetoresistive element, the first layer including at least one of thealloys and having a thickness of 3 nm or more, and the second conductivelayer includes a third layer and a fourth layer, the third layer beingdisposed on a side of the second magnetoresistive element, the thirdlayer including at least one of the alloys and having a thickness of 3nm or more.